1. Technical Field
The present invention relates to techniques for detecting and reducing defects formed on a wafer during submicron lithography.
2. Description of the Related Art
Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects on integrated circuits. Defects are the primary "killers" of devices formed during manufacturing, resulting in yield loss. Hence, defect densities are monitored on a wafer to determine whether a production yield is maintained at an acceptable level, or whether an increase in the defect density creates an unacceptable yield performance. Hence, the detection and monitoring of defects is critical to maintaining an acceptable yield.
As device geometries shrink into the sub-half micron regime, controlling and reducing defect levels become increasingly important in both research and development and manufacturing environments. Any delay in addressing the causes and cures of these yield killers can prolong the development cycle and production release of new product technologies. However, defect evaluation for a new lithography process on product wafers is difficult due to metrology limitation, substrate noises and previous layer defects. This problem is particularly pronounced for backend layers where differences in the metal grain sizes and reflectivity can confound defect inspection tools and can be picked up as false defects. Often yield learning is long delayed awaiting sort data, before lithographers can determine the beneficial effects of proposed manufacturing improvements.
During the qualification stage of a new process technology or a new product, a minimum sort yield level (typically 15 to 20%) must be achieved in order for the new product or the new process to be considered production worthy. Often, managers use the early yield indicator to decide whether to utilize a new product design or a new process technology. However, IC device yield is largely influenced by defects in the fabrication process. Defects are commonly divided into two categories by yield engineers: systematic and random. Systematic defects are anomalies resulting from an unoptimized process flow, from design rule violations or a mismatch between process and design in the worst case. However, once a systematic defect is identified, its impact on product yield and performance is predictable and therefore can be corrected within a short time. On the other hand, random defects are due to contamination from process and equipment. They occur irregularly and tend to be unpredictable. Elimination of these random defect excursions, if not controlled and monitored properly, become more difficult and can confound systematic yield issues. If random defects cannot be reduced in a timely manner, a new process can be jeopardized and consequently lead to a delay in new product introduction.
In the photolithography area, in-line defect monitoring of production wafers becomes more difficult with each successive masking layer. Film sensitivities, topographic effects and previous layer defects can make the determination of the existence or magnitude of photo process defect occurrence almost impossible. This is particularly true for the backend process where multi-layer metallization and chemical mechanical polish (CMP) are used. The effort to optimize a lithographic process can be statistically insignificant due to small sample size, or inconclusive if impacted by other non-photo variables.